First Workshop on
Computer Architecture and Operating System
co-design
In conjunction with:
the 5th International Conference on
High-Performance Embedded Architectures and Compilers (HiPEAC)
Pisa, Italy, January 25-27, 2010
Multi-core and/or multi-threaded architectures are monopolizing the market, from embedded systems to supercomputers. However, achieving high performance with these modern systems has become a complex task: as the number of cores per chip and/or the number of hardware threads per core continue to increase, new challenges arise in terms of scheduling, power, temperature, scalability, design complexity, efficiency, throughput, heterogeneity, etc. Performance is not the only important metric anymore, and new metrics (such as security, power, total throughput, Quality of Service) are becoming more and more important. It seems clear that neither the hardware nor the software alone can achieve the desired performance and, at the same time, be compliant with these constraints. The answer to these new challenges comes from hardware-software co-design. Computer Architectures (CA) and Operating Systems (OS) should interact through a well-defined interface, exchanging run-time information, monitoring application progress and needs, and enforcing resource management.
This workshop aims to bring together researchers and engineers from academia and industry to share ideas and research directions in Computer Architecture and Operating System co-design and interaction. Authors are invited to submit innovative manuscripts in all areas of parallel and distributed processing, real-time systems, HPC systems and commercial/server systems.
Topics of interest
Papers are sought on topics including, but not limited to:
- Architectural and OS support for power and thermal management
- Architectural and OS support for scheduling applications on emerging multi-core systems
- Benchmarking and characterization of OS activity in multi-core architectures
- Architectural and OS support for virtualization
- Architectural and OS support to manage processor resource allocation and heterogeneity for Quality of Service
- Simulation tools for full system simulation
The workshop provides a forum to discuss the latest proposals in computer architecture and OS and to bring ideas and research problems to the attention of the audience.
We will prioritize papers reporting from on-going work that address cross-cutting issues and provide thought-provoking insights into the main themes. Proceedings with accepted papers will be made available at the workshop.
Advanced Program
| 9.00-9.15 | Opening |
| 9.15-10.15 | Keynote: Blue Gene: Building a Highly Scalable and Reliable Supercomputer Using Embedded Cores: Focus on Software
Robert Wisniewski (IBM Research - Watson) In 2004, Blue Gene made a significant impact by introducing an ultra-scalable computer with a focus on low power. After that, Blue Gene/L maintained the number 1 spot on the top500 list for an unprecedented 7 lists. Both the hardware and software of Blue Gene has been designed with an emphasis to use little power, occupy a small footprint, and scale to massive number of cores. I will describe the Blue Gene/P hardware and describe the software that runs on it. I will describe the design philosophies that have allowed the team to produce a machine that scales to the large number of cores. I will discuss the challenges faced, and provide thoughts on the upcoming challenges in the next generation. |
| 10.15-10.30 | Coffee break |
| 10.30-11.00 | Discovering hypervisor overheads using micro and macrobenchmarks
A. Bastoni (SPRG - University of Rome Tor Vergata), D.P. Bovet (SPRG - University of Rome Tor Vergata), M. Cesati (SPRG - University of Rome Tor Vergata), P. Palana (SPRG - University of Rome Tor Vergata) |
| 11.00-11.30 | A Unified Operating System for Clouds and Manycore: fos
D. Wentzlaff (MIT), C. Gruenwald (MIT), N. Beckmann (MIT), K. Modzelewski (MIT), A. Belay (MIT), L. Youseff (MIT), J. Miller (MIT), A. Agarwal (MIT) |
| 11.30-12.00 | Composable processor virtualization for real-time embedded systems
A. Milutinovic (U Twente), A. Molnos (TU Delft), K. Goossens (TU Delft, NXP Semiconductors), D. She (TU Eindhoven) |
| 12.00-12.15 | Closing |
Important dates
| Abstracts submission deadline: | November 6, 2009 (Extended) |
| Papers submission deadline: | November 6, 2009 (Extended) |
| Notification to authors: | December 20, 2009 |
| Final version of accepted papers: | January 3, 2010 |
| Workshop: | January 23, 2010 |
Paper submission
Submitted papers should use the LNCS format and should be 10 pages maximum. Manuscript preparation guidelines can be found at the LNCS web site.
In order to submit your paper go to
this page.
Organizers
| Francisco J. Cazorla | Barcelona Supercomputing Center | Spain | francisco.cazorla[at]bsc.es |
| Roberto Gioiosa | Barcelona Supercomputing Center | Spain | roberto.gioiosa[at]bsc.es |
Program committee
| David Atienza | Ecole Polytechnique Federale de Lausanne | Switzerland |
| Alper Buyuktosunoglu | IBM Research - Watson | USA |
| Marco Cesati | University of Rome "Tor Vergata" | Italy |
| Sandhya Dwarkadas | University of Rochester | USA |
| Ayose Falcon | HP Labs | Spain |
| Alexandra Fedorova | Simon Fraser University | Canada |
| Isaac Gelado | Universitat Politècnica de Catalunya | Spain |
| Sally McKee | Chalmers University of Technology | Sweden |
| Ron Minnich | Sandia National Lab | USA |
| Dan Tsafrir | Technion - Israel Institute of Technology | Israel |
| Rizos Sakellariou | University of Manchester | UK |
| Oreste Villa | Pacific Northwest National Laboratory | USA |
Webmaster: roberto.gioiosa[at]bsc.es